Microcontroller Direct Memory Access (DMA): Architecture, Behavior, and Practical Design Considerations

This document provides a comprehensive, deeply detailed explanation of Direct Memory Access (DMA) in microcontrollers, how it interacts with peripherals, how it differs from PC‑class DMA, and why it is essential for real‑time audio and display systems such as a professional audio diagnostic tool. This is preliminary research that I'm doing. I'm 100% new to this technology, so anything I say here could be wrong!

1. Microcontroller DMA Basics

This section consolidates all DMA‑related concepts into a clear, structured overview.

1.1 What DMA Is

Direct Memory Access (DMA) is a dedicated hardware subsystem inside a microcontroller that autonomously moves data between memory and peripherals without CPU involvement.
The DMA controller is a separate hardware block on the same silicon die as the CPU, functioning like a high‑speed data‑moving co‑processor.

1.2 Why DMA Exists

Without DMA

• CPU must manually move every byte
• Audio sampling becomes jittery
• Display updates block the CPU
• Real‑time tasks interfere with each other

With DMA

• Audio samples stream reliably
• SPI displays update smoothly
• CPU is free for DSP, UI, and logic
• System feels responsive and professional

1.3 How the CPU Configures the DMA Controller

The CPU configures DMA by writing to memory‑mapped hardware registers. These registers are not RAM — they are hardware control points.

Example (simplified):

• 0x400E8000 → DMA_SOURCE_ADDRESS
• 0x400E8004 → DMA_DESTINATION_ADDRESS
• 0x400E8008 → DMA_TRANSFER_SIZE
• 0x400E800C → DMA_CONTROL

Once configured and started, the DMA controller operates autonomously.

1.4 How DMA Works (Step‑by‑Step)

1. Driver code runs on the CPU.
2. Driver writes DMA configuration registers:
   • Source address
   • Destination address
   • Transfer size
   • Transfer width
   • Trigger source
   • Increment rules
3. CPU sets a “start” bit.
4. DMA engine takes over and performs the transfer.
5. DMA raises an interrupt when done.

1.5 DMA and Peripherals

Many DMA transfers are peripheral‑triggered, meaning the peripheral signals when data should be moved:

• SPI → triggers DMA when TX FIFO is empty
• I2S → triggers DMA when a sample arrives
• ADC → triggers DMA when a conversion completes

This ensures DMA moves data only when the peripheral is ready.

1.6 DMA in Audio (I2S)

A typical I2S audio pipeline:

• I2S receives audio samples
• I2S triggers DMA
• DMA writes samples into RAM
• CPU wakes only when a full buffer is ready

This architecture ensures zero‑jitter audio and predictable DSP timing.

1.7 DMA in Displays (SPI or RGB)

A typical display update pipeline:

• CPU prepares a pixel buffer
• CPU configures DMA
• DMA streams pixels to SPI or RGB interface
• CPU continues running UI and DSP
• DMA interrupts CPU when done

This enables smooth FFT bars, waveform rendering, and real‑time UI updates.

1.8 Protections Against DMA Corruption

DMA is powerful, but microcontrollers include multiple safeguards:

1. Memory map boundaries
2. Peripheral‑triggered pacing
3. Explicit transfer size limits
4. Circular mode is opt‑in
5. Bus arbitration rules
6. Error and completion interrupts
7. Software discipline (correct buffer sizes, addresses, increments)

These protections make DMA reliable even in complex real‑time systems.

1.9 Do Most Microcontrollers Have DMA?

• 8‑bit MCUs: usually no DMA
• Mid‑range 32‑bit MCUs: basic DMA
• High‑performance MCUs (Teensy 4.1, STM32H7): advanced DMA with many channels and triggers

The Teensy 4.1 is particularly well suited for real‑time audio + graphics.

1.10 DMA and SPI/Parallel Interfaces: Hardware‑Level Coordination

DMA is a hardware mechanism that autonomously moves data between memory and peripherals. SPI and parallel interfaces are communication protocols — they do not provide DMA themselves.

How coordination works

• CPU configures DMA registers
• DMA moves data into the peripheral’s FIFO or registers
• The peripheral handles serialization (SPI) or parallel timing
• DMA and the peripheral coordinate via hardware triggers and bus arbitration

Key points

• DMA is a microcontroller feature
• SPI/parallel are protocols
• RA8875 has no DMA; the MCU’s DMA feeds it
• This is hardware‑level coordination, not a software trick

Once started, DMA remains actively involved for the entire transfer.

1.11 Parallel vs. Serial DMA Modes

Parallel Interface Mode

• Peripheral connects directly to MCU data bus
• Multiple bits transferred simultaneously
• High throughput, low latency
• Often called “memory‑mapped” or “bus‑master DMA”

Serial Interface Mode (SPI)

• No direct bus access
• Data serialized bit‑by‑bit
• DMA feeds the peripheral’s FIFO
• Peripheral handles protocol timing

Comparison

Design implications

• Parallel = speed
• Serial = simplicity
• DMA enhances both, but differently

1.12 DMA Controller Active Role During Transfers

During a transfer, DMA:

• Arbitrates bus access continuously
• Responds to peripheral triggers
• Manages address increments and byte counts
• Handles circular/linear modes
• Interrupts CPU only on completion or error

This enables concurrent audio + display streaming without CPU burden.

1.13 Capacity and Limitations of DMA Controllers

DMA is powerful but finite:

• Channels: limited number
• Bus bandwidth: shared with CPU
• Priority/arbitration: contention possible
• Peripheral triggers: simultaneous triggers require careful design

Designers use circular buffers, double buffering, and priority tuning to maintain real‑time performance.

1.14 Monitoring DMA Activity

DMA controllers rarely expose utilization counters. Engineers rely on indirect indicators:

• DMA status registers
• Transfer completion interrupt frequency
• Peripheral FIFO levels
• CPU load and bus contention
• External bus analyzers (advanced systems)

Profiling and stress testing are essential.

1.15 CPU Bus Wait Time Due to DMA Activity

CPU wait time can be evaluated by:

• Bus arbitration behavior
• CPU stall cycle counters
• Interrupt latency
• Logic analyzer bus traces
• Cache hit/miss behavior

Understanding bus wait time helps optimize DMA priorities and prevent underruns or glitches.

1.16 Evaluating Microcontroller DMA Capabilities

Key factors to examine:

1. Number of DMA channels
2. Supported transfer types
3. Peripheral trigger integration
4. Addressing modes
5. Transfer width and size
6. Bus arbitration and priority
7. FIFO/buffering support
8. Error/interrupt support
9. Scatter‑gather or linked‑list capability
10. Power/clocking behavior
11. Documentation and examples

DMA capability varies widely across MCU families.

2. Summary

A professional audio diagnostic tool requires:

• High‑quality external ADC
• Proper analog front end
• DMA‑driven audio + display architecture
• IPS display
• Multi‑mode windowing system

The Teensy 4.1 excels due to:

• 600 MHz Cortex‑M7
• 32‑channel advanced DMA
• I2S audio support
• Fast SPI/RGB display interfaces

This architecture supports real‑time audio visualization, FFT analysis, signal generation, MIDI interpretation, and cable diagnostics.

The Teensy 4.1 can comfortably handle 44.1 kHz audio streaming and 60 FPS visualization simultaneously when buffers and priorities are well managed.

3. Microcontroller DMA vs. PC DMA

Microcontrollers use a centralized DMA controller.
PCs use distributed DMA engines inside each peripheral.

3.1 How DMA Works on a PC

1. Each major peripheral has its own DMA engine (NVMe, GPU, NIC, etc.)
2. Devices compete for bus access through structured PCIe arbitration
3. CPU configures DMA by writing buffer addresses into device registers
4. Device DMA engines perform transfers autonomously
5. IOMMU enforces DMA safety boundaries

PC DMA uses scatter/gather descriptors and multi‑queue engines.

3.2 Accuracy of Understanding

Correct

• Peripherals have their own DMA engines
• They compete for bus access
• Arbitration determines access
• DMA is distributed

Refinements

• PCIe arbitration is structured
• CPU does not configure a central DMA controller
• IOMMU protects memory
• Devices use descriptor tables

3.3 Side‑by‑Side Comparison

Key Idea

Microcontrollers use centralized DMA.
PCs use distributed DMA, coordinated by PCIe and protected by the IOMMU.